Breakout Board¶

This device provides user-facing access for headstage, miniscope, and auxiliary data IO.

Design Repository: https://github.com/open-ephys/onix-breakout
Compatibility: PCIe Host, Headstage-64, Neuropixels-1.0 Headstage, Miniscopes

Overview¶

The ONIX Breakout Board allows bench access to the IO provided by the PCIe Host.

ONIX Breakout Board v1.5.¶

The Breakout Board provides access to the following IO:

4x headstage port feed-throughs, each with a power switch
3x, passive, high-speed clock feed-throughs
12x passive, ESD-protected, analog feed-throughs.
BNC, ribbon, or direct wire access to 12 analog inputs or outputs
Ribbon cable or direct, wire-access to 8 digital outputs and 8 digital inputs. These are 5V compliant.
HARP bus controller

Additionally, it has the following features:

Lots of indication LEDs
6 buttons for marking experimental events for communication and programming.
Rugged M6 and 1/4-20 mounting holes for both metric and imperial optical tables
19” rack compatibility
Fully open-source gateware and made using an open-source FPGA toolchain (yosys & nextpnr)

Synchronizing Multiple PCIe Hosts

Setup